| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a static clock pulse generator comprising a plurality of stages, each of which comprises a D-type flip-flop and a gating circuit. <P>SOLUTION: In the static clock pulse generator comprising main clock input and N stages, the i-th stage of the generator comprises a D-type circuit having reset input for receiving a reset signal from the (i+a)-th (here, a is ≥1) stage and data input and the gating circuit 4 having an output for supplying a pulse to the data input in response to the D-type circuit output signal at the (i-1)-th (here, 1<i≤(N-a)) stage and a clock pulse at the main clock input. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
