| 摘要 |
FIG. 1 c shows a logic tree 10 c comprising a plurality of logic paths ( 27, 29, 31, 33 ) connected at a root 11 c. The length of each path represents the delay of the path at a nominal supply voltage. The voltage supply structure for the logic tree 10 c is partitioned as shown in FIG. 3 c, according to the delay of each logic path. For example, logic path ( 29 ) having the worst-case delay is supplied a voltage level V 1 , for example the nominal supply voltage. Logic paths ( 27 ) and ( 31 ), having a shorter delay, are supplied a second voltage level V 2 , which is lower than the first voltage level V 1 . Logic path ( 33 ), having an even shorter delay, is supplied a third voltage level V 3 , which is lower than V 2 and V 1 . The voltage structure enables the voltage level and hence power consumption to be reduced without increasing the overall worst-case delay of the logic tree 10 c.
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