Phase-locked loop with a digital calibration loop and an analog calibration loop

摘要

A phase-locked loop (PLL) architecture ( 100 ) is provided that includes a voltage-controlled oscillator (VCO) ( 116 ). The PLL architecture ( 100 ) also includes a digital calibration loop ( 132 ) coupled to the VCO ( 116 ). The digital calibration loop ( 132 ) implements a digital filter ( 126 ) to provide a digital control to the VCO ( 116 ) for centering a VCO frequency output. The PLL architecture ( 100 ) also includes an analog calibration loop ( 130 ) coupled to the VCO ( 116 ). The analog calibration loop ( 130 ) provides an analog control to the VCO ( 116 ) for adjusting the centered VCO frequency output.