| 摘要 |
A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an immediate which specifies the shift count N and the processor derives a third added 2<SUP>N-1</SUP>, and the ADDSRN instruction is used in accelerating digital signal processing code sequences of the form <?in-line-formulae description="In-line Formulae" end="lead"?>dest:=(A+B+C+D . . . +M+2<SUP>N-1</SUP>)>>N <?in-line-formulae description="In-line Formulae" end="tail"?> |
