| 摘要 |
PROBLEM TO BE SOLVED: To efficiently recover transfer errors in a bus access, and to enhance transfer accuracy. SOLUTION: A bit for indicating the generation of a data parity error is formed in a control register 17, status of the parity error bit indicates the error, sequence number is written in an error status area of the control register 17, and the error is notified to a main board 5, when the data parity error is generated in a bus interface 14 in bus master thereof. Data, generating the transfer error, are thereby retransmitted to a subsystem module with respect to the sequence number written in the error status area of the control register 17, in a main board 5 side receiving error notification, and the transfer error in the bus access is recovered efficiently, thereby enhancing the transfer accuracy. COPYRIGHT: (C)2006,JPO&NCIPI
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