| 摘要 |
A voltage level shifter is disclosed, comprising an inverter converting an input signal to an inverted signal, a first NMOS transistor coupled to a first PMOS transistor through a second gating device, and a second NMOS transistor coupled to a second PMOS transistor through a first gating device. Gates of the first and second NMOS transistors are coupled to the input signal and the inverted signal respectively, and gates of the first and second PMOS transistors are coupled to sources of the second and the first NMOS transistor respectively, with the source of the second NMOS transistor acting as the output terminal of the voltage level shifter. The first/second gating device restricts leakage current from the second/first PMOS transistor to the second/first NMOS transistor when the logic state signal is switched, such that the voltage level shifter can be operated with an increased output/input voltage ratio.
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