| 摘要 |
A clock driver of an IC device is provided to facilitate the synchronization of an oscillator frequency and inner signals and to design the circuit when designing inner circuit, regardless of a main frequency. A first flip-flop(12) outputs a first clock signal which is divided into two portions on basis of high edge of clock signal. A second flip-flop(15) outputs a second clock signal which is divided into two portions on basis of low edge of clock signal. A first logic gate(13) provides a third clock signal of high level when the first clock signal and the second clock signal are different logic levels. A counter outputs a counting signal by using the third clock signal. A second logic gate compares the counting signal with an input signal having the information of division rate and outputs a detect signal when the counting signal maintains the same value of the input signal. A timing block outputs a counter clock reversing at the high edge period of the detect signal. |
