| 摘要 |
PROBLEM TO BE SOLVED: To obtain a signal of a desired format without changing a ride to a clock rate higher than a clock rate before and after format conversion. SOLUTION: A scan converting circuit 20 applies interpolation processing to interlace signals DGi, DRi, DBi of a first clock rate and simultaneously generates signals of odd-numbered and even-numbered lines to perform scan conversion into progressive signals DGp-O, DGp-E, DRp-O, DRp-E, DBp-O, DBp-E of the first clock rate. A resolution converting circuit 25 uses the progressive signals of the first clock rate to perform horizontal resolution conversion and vertical resolution conversion and generates signals DGpc, DRpc, DBpc of a second clock rate that is a desired resolution. COPYRIGHT: (C)2006,JPO&NCIPI
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