| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout design method of a semiconductor integrated circuit capable of reducing electric noise as compared with a conventional one. SOLUTION: For the function block of each function, the library of the function block is prepared. The library of the function block has a plurality of kinds of capacitors where capacities of added on-chip capacitors are different from one another. For the function block of each function, arrangement is examined while the library of the function block with the capacitor having the maximum capacity in respective libraries is selected. Only when it is determined that the arrangement result does not meet a prescribed constraint, the capacity of the added on-chip capacitor is successively reduced, and the arrangement of the function block with the capacitor is examined. COPYRIGHT: (C)2006,JPO&NCIPI
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