| 摘要 |
PROBLEM TO BE SOLVED: To provide a high breakdown voltage MOS transistor having a low concentration diffusion layer which overlaps a region near the end of a gate electrode in a self-alignment process manner and works as a field alleviating layer, and to provide a method of manufacturing it. SOLUTION: First and second low concentration diffusion layers 104-2 and 104-3 which are worked as the field alleviating layer and the gate electrode 111 are formed so that a first insulating pattern 102 is used in a self-alignment process manner as a common mask. The widths of the first and second low concentration diffusion layers 104-2 and 104-3 which are operated as the field alleviating layer correspond to the widths L1 and L3 of the space of the first insulating film pattern, and correspond to the amount of gate overlap. Accordingly, the field alleviating layer having the amount of gate overlap defined by the widths L1 and L2 of the space of the first insulating film pattern is formed in the self-alignment process manner in the gate electrode 111. COPYRIGHT: (C)2006,JPO&NCIPI
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