METHOD OF FABRICATING SEMICONDUCTOR DEVICE

摘要

A method for manufacturing a semiconductor device is provided to obtain an aiming degree of planarization from an interlayer dielectric structure by performing a high temperature reflow process without the degradation of source/drain profiles using an enhanced fabrication order. A gate electrode pattern is formed on a semiconductor substrate(210) with an active region. An interlayer electrode is formed on the gate electrode pattern. A contact hole for exposing partially the gate electrode pattern is formed at both sides of the gate electrode pattern by performing an area type etching process on the interlayer dielectric of the active region. Then, source/drain regions are formed in the substrate by performing an ion implantation through the contact holes.