| 摘要 |
A flip-flop with improved operation speed is provided to reduce the output delay time due to a circuit logic added to obtain the reset or the set function. A flip-flop with improved operation speed comprises a switching unit(410), a latch unit(420) and a reset controller(430). The switching unit(410) transmits the data to a first node(N1) in response to a clock signal(CLK). The switching unit(410) transmits the data to the first node(N1) in response to a first level of the clock signal(CLK) and transmits the data of the first node(N1) in response to a second level of the clock signal(CLK). The latch unit(420) latches the data of the first node(N1) to a second node(N2) in response to the clock signal(CLK) and outputs the data through an output nod(NOUT). The reset controller(430) resets the output node(NOUT) in response to the reset control signal(RST). The reset controller(430) is connected between the second node(N2) and a first voltage(VSS) and includes a transistor(RTR). The transistor(RTR) receives an inverting signal of the reset control signal(RST) at a gate.
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