| 摘要 |
<p>[PROBLEMS] To provide a field effect transistor capable of reducing the ON resistance while maintaining the OFF voltage resistance. [MEANS FOR SOLVING PROBLEMS] A field effect transistor (FET) includes a carrier travel layer (23)in layered structure (20) formed by a plurality of nitride semiconductor layers and has a gate electrode (186), and a source electrode (185) and a drain electrode (187) sandwiching the gate electrode arranged on the layered structure. The layered structure has a stepped portion having a side surface (140e) for exposing the end portion of the carrier travel layer at both sides of the gate electrode. A part of the electrode on the stepped portion side surface is arranged on the front surface of the stepped portion upper step (140t). A part of each electrode is arranged on the upper stage. The distance L in the carrier direction from the side surface to each electrode end of the gate electrode side is L = 10µm . In the range where the L[µm] is from 1 to 10, the contact resistance of the source and drain electrode R<SUB>c</SUB>[O·mm] by the TLM method at distance L is a value lower than the segment of (L, Rc) = (1, 2) and (10, 5).</p> |
