| 摘要 |
A DRAM cell including a trench capacitor structure, a transistor and a stacked capacitor structure is provided. A first electrode of the trench capacitor structure is disposed in the substrate at the bottom of a trench. A second electrode of the trench capacitor structure is disposed in the trench. The transistor includes a gate, first and second source/drain regions. The gate is disposed on the substrate beside the trench capacitor structure. The first and the second source/drain regions are disposed in the substrate on respective sides of the gate. A third electrode of the stacked capacitor structure is disposed on the substrate between the gate of the transistor and the trench capacitor structure. A fourth electrode of the stacked capacitor structure is disposed on the third electrode above the substrate. The first electrode connects electrically with the fourth electrode, and the second electrode connects electrically with the third electrode.
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