发明名称 Synchronization method and program for a parallel computer
摘要 Barrier synchronization between multiprocessors is performed at high speed while reducing overhead of parallel processing without adding any special hardware mechanism. A parallel computer synchronization method is provided to synchronize threads through barrier synchronization for parallel execution of plural threads on plural processor modules. The parallel computer has plural processor modules (P 0 and P 1 ) equipped with plural processor cores (cpu 0 to cpu 3 ). The processor cores are each assigned plural threads (Th 0 to Th 7 ) to execute multithread processing. The plural threads (Th 0 to Th 7 ) are set in hierarchical groups (Gr), and barrier synchronization is performed on each group separately.
申请公布号 US2006212868(A1) 申请公布日期 2006.09.21
申请号 US20050312345 申请日期 2005.12.21
申请人 TAKAYAMA KOICHI;AOKI HIDETAKA 发明人 TAKAYAMA KOICHI;AOKI HIDETAKA
分类号 G06F9/46 主分类号 G06F9/46
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