| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a page buffer circuit of a flash memory device in which power consumption can be reduced in a standby mode. <P>SOLUTION: The page buffer circuit of the flash memory apparatus comprises a cache register circuit in which program data are stored at the time of program operation, a main register circuit in which in response to a main latch signal, first state data corresponding to read-out data received from bit lines through a sensing node at the time of read-out operation are stored, or second state data corresponding to program data received from a cache register circuit through the sensing node at the time of program operation are stored, and a power source supply circuit supplying first and second voltages to the main register circuit and the cache register circuit as operation voltages in an active mode, and supplying third voltages to the main register circuit and the cache register circuit as operation voltages in a standby mode. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
