发明名称 DEVICE, METHOD, AND PROGRAM FOR SUPPORTING GENERATION OF TEST PATTERN
摘要 PROBLEM TO BE SOLVED: To shorten the turn around time (TAT) and to improve the detection rate in the transition delay examination. SOLUTION: In the test pattern generation supporting device 310, if the acquisition part 311 acquires the connection information 301 of testing circuit 200 and a path exempt out of test, the detection part 312 detects paths between all FFs constituting the test objective circuit 200, and forms the extra test objective path list 400. The test path extraction part 313 extracts the testing path and forms the testing path list 500. The searching part 314 forms the searching result list 600. The extra test objective cell extraction part 315 extracts extra test objective cell, turns the finish flag of the extra test objective path including extracted extra test objective cell from "0" to "1". In the case, the finish flag of extra test objective path list 400 are turned to "1", the correction part 316 corrects the connection information 301 so as to insert the dummy buffer into the data pins of the extra test objective cells. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006250651(A) 申请公布日期 2006.09.21
申请号 JP20050066232 申请日期 2005.03.09
申请人 FUJITSU LTD 发明人 KARASAWA NAOKO;KONISHI HIDEAKI;KATO HIROKO
分类号 G01R31/3183;H01L21/822;H01L27/04 主分类号 G01R31/3183
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