| 摘要 |
PROBLEM TO BE SOLVED: To suppress the generation of ruggedness on a line edge of a gate electrode in the gate lengthwise direction in pattern formation by the etching of the gate electrode using a polysilicon. SOLUTION: An SOG (spin-on-glass) layer to be a first hard mask layer and a CVD formation silicon oxide film layer to be a second hard mask layer are successively laminated on a polysilicon layer, and the gate electrode of the polysilicon is patterned by etching. Consequently, a phenomenon can be sharply suppressed that ruggedness may be generated on the line edge of the gate electrode due to etching using a silicon oxide film hard mask layer having ruggedness caused by wavy ruggedness generated on the surface of the polysilicon layer in a conventional method. COPYRIGHT: (C)2006,JPO&NCIPI
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