发明名称 DIGITAL SIGNAL RECEIVING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a digital signal receiving circuit capable of reproducing a baseband signal correctly, even if direct-current potential offset arises to a demodulation signal. <P>SOLUTION: A peak level of an incoming signal IN is detected at the timing which is late for a peak detecting part 11 by a delay peak detecting part 13 so that a peak difference PLD between a delay peak level DPL and a peak level PL may be detected by a peak difference detecting part 15. In a reset part 17, a reset signal BRS to a bottom detecting part 12 is outputted, when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value corresponding to the amplitude of the incoming signal IN and the peak difference PLD exceeds a permissible peak difference PLM. Thereby, the bottom level BL output from the bottom detecting part 12 is transposed to a bottom level based on the newest incoming signal IN. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006254143(A) 申请公布日期 2006.09.21
申请号 JP20050068506 申请日期 2005.03.11
申请人 OKI ELECTRIC IND CO LTD 发明人 MIZUNAGA SUNAO;MURAKAMI TADAMASA
分类号 H03K5/08;H03K5/153;H03K5/1532 主分类号 H03K5/08
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