| 摘要 |
<P>PROBLEM TO BE SOLVED: To execute certainly verification of complicated system operation by holding access patterns of all bus-masters which can be realized in a bus protocol. <P>SOLUTION: A circuit of this invention is provided with a master 12 for test which outputs test patterns for operation verification toward slaves to a system bus 16 and receives response signals from the slaves, a means 13a which holds test patterns and corresponding expected values, and a comparison means 13b; and is also provided with a BIST (Built-in Self-test) and memory circuit 13 having a function which compares the response signals from the slaves at the time when the test patterns are outputted through the master for test 12 with the expected values, and a BIST interface circuit 14 for inputting the test patterns and the expected values to the holding means through an external interface 15. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
