| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a logical-address/physical-address conversion function in one chip while suppressing increase of chip area. <P>SOLUTION: The apparatus is provided with a plurality of blocks including respectively word lines to which memory cells are connected, a row decoder selecting a word line, and a block decoder selecting a block, the block decoder includes a logic address register 31 holding logic block addresses corresponding to a plurality of blocks and a status register 32 holding block status, and selects the corresponding block when the inputted logic address and the status to be accessed coincide with the logic block address held in the registers 31, 32 and the block status. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
