发明名称 Block decoding methods and apparatus
摘要 In an embodiment, a method includes performing a redundancy check to determine if a baseline bit sequence is compliant. When the baseline bit sequence is not compliant, the method additionally includes performing an iterative process until a compliant, candidate bit sequence is identified. The iterative process includes identifying one or more existing branches within a conceptual tree diagram, calculating scores for potential paths branching from the one or more existing branches, and performing a subsequent redundancy check on a next candidate bit sequence, which corresponds to a potential path that has a next lowest score, to determine if the next candidate bit sequence is compliant.
申请公布号 US2006212784(A1) 申请公布日期 2006.09.21
申请号 US20050084502 申请日期 2005.03.18
申请人 INTEL CORPORATION 发明人 GRINIASTY MEIR;ALTAHAN MOTI
分类号 H03M13/03 主分类号 H03M13/03
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