| 摘要 |
Method for transfer of data over a data bus (13) between a processor (10) and a memory unit (19) with a number of memory cells (17). The processor transmits the logical address of a memory cell via an address bus (11). The memory cell has at least two different logical addresses assigned to it and the transferred data is altered in a manner dependent on the logical address allocated to it. The data is changed using a logic circuit, data bit permutations, data bit replacements with address bits, or cryptographically determined replacements. The data change is different for each memory access. An Independent claim is made for a data transfer system with a data changing unit for varying manipulation of transmitted data. |
