Synthesizable vhdl model of a multi-channel dma-engine core for embedded bus systems

摘要

A synthesizable VHDL model of a multi-channel DMA-engine for use in embedded bus systems, called the Acorn DMA Engine is described. Said invention features a controller capable of interleaving up to 16 channels for data-transfers over a single 32-bit AHB bus, using a two-tier, programmable-priority, round-robin TDM algorithm. Single-block, multi-bock and scatter-gather transfers are supported and the DMA engine allows reprogramming and/or retriggering any of the 16 channels while other transfers are under way, without wait-states introduced onto the bus. Special circuitry is provided to minimize transfer-time of the 32-bit bus, even for addresses not aligned on 32-bit word boundaries, by automatically adjusting data-transfer size at every bus-cycle. IRQs are issued at transfer end, or to signal programming/runtime errors. IRQ-vectors that carry information associated with the interrupt are stored in either of two 8-entry queues, allowing the Acorn DMA Engine to continue operating even while other IRQ-vectors are still pending for service by the system host(s). The Acorn DMA Engine is supplied in the form of synthesizable VHDL code for incorporation into embedded/Soc designs. For attachment onto an AHB bus it requires the use of standard AHB master and slave interfaces.