| 摘要 |
A differential digital-to-analog voltage converter (VDAC) includes, in part, a resistor, and at least two decoding stages. The resistor is divided into N equal segments each disposed in a different one of N decoders forming a first decoding stage. The resistor segment in each decoder is further divided into M equal segments to provide M tapped nodes. Each decoder of the first decoding stage delivers two of the M tapped voltages to a pair of associated output nodes, and that are complementary with respect to a voltage present at the center of the resistor segment disposed in that decoder. A second decoding stage receives the first and second voltages delivered by each of the N decoders and delivers two of these voltages, that are complementary with respect to a voltage present at the center of the resistor, to a pair of third and fourth output nodes.
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