| 摘要 |
A CAM block includes a CAM array having a plurality of rows and columns of 4-bit NAND-type CAM cells therein. Each of a plurality of the NAND-type cells includes a respective ladder-type compare circuit having four two-transistor rungs. At least one of the plurality of rows includes a first 4-bit NAND-type CAM cell having a first ladder-type compare circuit with four two-transistor rungs and a second 4-bit NAND-type CAM cell having a second ladder-type compare circuit with four two-transistor rungs. A match line segment is also provided, which is connected to four source terminals of transistors in the first ladder-type compare circuit and four drain terminals of transistors in the second ladder-type compare circuit.
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