| 摘要 |
While a memory section ( 1 ) is in standby mode, a power supply/interruption circuit ( 2 ) supplies electric power to a memory section ( 1 ) only during periods in which a refresh operation is performed in synchronization with a timing of the refresh operation generated by the clock circuit ( 3 ), and interrupts power supply to the memory section ( 1 ) during periods in which the refresh operation is not performed. Thus, power consumption of the memory section that performs the refresh operations is suppressed, by which a power consumption reduction of the semiconductor storage device is realized. |
