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发明名称
记忆电路
摘要
防止存取时间变长,且,使软体错误的发生频率在实际使用上降得充分低的记忆体电路。作为记忆体电路,包括:收存资料和为对上述资料进行纠错之冗长资料之资料收纳部;在没有从外部接受到输出入资料的存取命令时,对上述资料收纳部之资料,用上述冗长资料,至少进行错误检测,还至少将得到的结果作为错误检测信号输出之纠错部。当接到输出收存之资料的存取命令时,被指定之资料不经过上述纠错部之处理直接被输出外部。
申请公布号
TW200632927
申请公布日期
2006.09.16
申请号
TW095102833
申请日期
2006.01.25
申请人
松下电器产业股份有限公司
发明人
铃木利一
分类号
G11C29/00
主分类号
G11C29/00
代理机构
代理人
许峻荣
主权项
地址
日本
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