| 摘要 |
PROBLEM TO BE SOLVED: To solve the following problem: an increase of a design TAT or power consumption cannot be suppressed, in a method performing the timing analysis of the whole circuit after suppressing a clock skew value as thoroughly as possible so as to guarantee the operation timing of the circuit, in the design of the semiconductor integrated circuit. SOLUTION: This design method includes: steps (S4-S5) for extracting a delay value of the whole clock route and calculating an average value of the delay value; steps (S6-S7) for setting a value obtained by subtracting a hold time of a reception side synchronous circuit cell from a data delay value between some synchronous circuit cells as an safe area about a hold error, and determining an area from which a clock skew value between the synchronous circuit cells is protruded from the safe area as a risk area of the hold error; and steps (S9-S10) for executing capacity extraction, delay calculation, and a static timing analysis only about the synchronous circuit cell corresponding to the risk area. A circuit configuration of the clock route is investigated from a degree of the risk area (step S8). COPYRIGHT: (C)2006,JPO&NCIPI
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