| 摘要 |
PROBLEM TO BE SOLVED: To suppress surface roughness in etching of a Low-k insulating film. SOLUTION: An SiOC film 2 is etched to a laminate structure of a layer where Cu wiring on a lower layer side is formed, an SiC film 1, and an SiOC film 2 to form an opening 5 for via hole to the SiC film 1. After wiring trenches 6a, 6b communicating with the opening 5 are formed, the SiC film 1 on the bottom of the opening 5 is etched to form a via hole. Thereupon, a deposit film of etching products is formed on the surfaces of the via hole and the wiring trenches 6a, 6b. By this deposit film, the surface of the SiOC film 2 exposed to etching plasma is flattened in which film the via hole and the wiring trenches 6a, 6b are formed. Thereafter, formation of a Ta film and embedding of plated Cu are implemented to form the via and the Cu wiring on the upper layer side. COPYRIGHT: (C)2006,JPO&NCIPI |
