发明名称 PARALLEL AMPLIFIER CONFIGURATION WITH POWER COMBINING AND IMPEDANCE TRANSFORMATION
摘要 A power amplifier uses parallel amplification (102, 104 and 106) and at least two levels of power combining (108, 110, 112 and 118) to manage peak-to-peak voltage swings, so as to reduce the likelihood of voltage breakdown at individual transistors. Each level of power combining provides an upward impedance transformation. For example, both levels of power combining may double the impedance output relative to the impedance input, so that the impedance at the amplifier output (114 and 120) is four times the input impedance. For an embodiment in which the second level is a quadrature power combiner (112), load reflections of the amplifier may be terminated at an isolation port (116 and 132). In addition, energy levels of the load reflections may be monitored (144).
申请公布号 WO2006014501(B1) 申请公布日期 2006.09.14
申请号 WO2005US24009 申请日期 2005.07.06
申请人 AMALFI SEMICONDUCTOR, INC.;BURNS, LAWRENCE, M.;WOO, CHONG, L. 发明人 BURNS, LAWRENCE, M.;WOO, CHONG, L.
分类号 H03F3/68 主分类号 H03F3/68
代理机构 代理人
主权项
地址