发明名称 Memory module and memory configuration with stub-free signal lines and distributed capacitive loads
摘要 In a memory module for a memory configuration having a bus system made up of a plurality of signal lines, each signal line has respectively been produced essentially without any stub continuously from a supplying contact device to a discharging contact device, disposed close to the supplying contact device, in order to increase a maximum data transmission rate within the memory configuration. Between the supplying contact device and the discharging contact device, each of the signal lines is routed in succession at minimum distances via connection elements associated with the signal line on memory chips associated with the signal line.
申请公布号 US2006202328(A1) 申请公布日期 2006.09.14
申请号 US20060431765 申请日期 2006.05.10
申请人 INFINEON TECHNOLOGIES AG 发明人 BRAUN GEORG;RUCKERBAUER HERMANN;KUZMENKA MAKSIM
分类号 H01L23/34;G11C5/04;G11C5/06;H05K1/14 主分类号 H01L23/34
代理机构 代理人
主权项
地址