A semiconductor package combines features of a molded array package (MAP) and a lead frame package. The package includes an electrically conductive substrate (32) that defines a grid of conductive pads which replace conventional leads. An integrated circuit chip is attached to the top surface of the lead frame, and output terminals of the chip are individually electrically communicated to selected connecting pads (42) of the lead frame grid array. Flip chips (64) and/or wire bond chips may be connected to the grid array. The grid pad is defined by channels that extend partway through the conductive substrate. The width of the channels increases from the top surface of the lead frame to the bottom of the channels (34), such that molding compound (50) is locked in place when it cures and hardens. The grid pads are singulated by sawing or etching channels from the bottom surface of the lead frame substrate that correspond to the channels defining the connecting pads on the top surface.
