发明名称 SAMPLE-AND-HOLD CIRCUITS
摘要 A sample-and-hold circuit including a first switch, a first capacitor and an amplifier is provided. The switch has a first terminal to receive the input signal and transmit it to a second terminal thereof in the sample period. The first terminal of the first capacitor couples to the second terminal of the first switch, and the second terminal of the first capacitor couples to a first voltage for storing the sampling result of the input signal. The amplifier couples to the second terminal of the first switch, wherein the amplifier is disabled in the sample period, and the amplifier is enabled to generate the output signal according to the sampling result in the hold period.
申请公布号 US2006202722(A1) 申请公布日期 2006.09.14
申请号 US20050161433 申请日期 2005.08.03
申请人 YEN CHIH-JEN;HSU CHIH-HSIN 发明人 YEN CHIH-JEN;HSU CHIH-HSIN
分类号 G11C27/02 主分类号 G11C27/02
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