| 摘要 |
861,509. Electonric counting-apparatus. GENERAL ELECTRIC CO. Ltd. July 17, 1959 [July 30, 1958], No. 24519/58. Class 106 (1). A binary or binary coded decimal counter employs a bi-stable transistor pair for each binary stage, the input pulses being supplied to both transistors of each stage under the control of gates. As shown, for a binary counter of four binary denominations, pulses to be counted from a source 1 are applied to a lead 11. The binary stages are generally similar, the second binary stage 3, for instance comprising cross-coupled transistors 7, 8, the transistor 8 being conducting to represent the digit " 0." Gating devices 9, 10, for the transistors 7, 8, are supplied with gating signals from networks 24, 25, the voltages applied to the bases of the transistors 26, 27, having one of two values depending on the conditions of the transistor 7 and the corresponding transistor 20 of the first binary stage 2, respectively, the gate 9 being opened to the passage of an input pulse only when both transistors 7 and 20 are conducting, i.e. when both stages register " 1." The network 25 comprises diodes 30, 31 and an emitter follower transistor 29, and the signal supplied thereby to the gate 10 renders the gate 10 conducting only when the transistors 8 and 20 are conducting. The controlling networks for the higher stages are similar. For the lowest stage, the gating devices 14, 15 for the transistors 15, 20 are controlled directly by the outputs of the respective transistors. For decimal counting, switches 33, 38 are changed over, the tenth pulse then causing the counter to be zeroized. Connections to further decimal orders may be made over terminals 52, 53. By combining outputs from the individual stages appropriately by means of gates, an electrical signal can be supplied when a predetermined count is reached. |
