发明名称 Side channel attack prevention in data processing apparatus such as a smart card
摘要 <p>Data processing apparatus is provided which comprises: a processor (5); memory (3); a scrambler (110) arranged on a data transfer path (114) between the processor (5) and the memory (3), for scrambling data items passing through the scrambler (110) according to a specified scrambling regime; and at least one designated control line (120) arranged between the processor (5) and the scrambler (110) for switching the scrambler (110) at least between operating according to a first scrambling regime and operating according to a second scrambling regime different to the first scrambling regime. The data processing apparatus is a smart card in the embodiment.</p>
申请公布号 GB2424089(A) 申请公布日期 2006.09.13
申请号 GB20050004825 申请日期 2005.03.09
申请人 SHARP KABUSHIKI KAISHA 发明人 ANTHONY KIRBY;JOHN PATRICK NONWEILER;SUSUSMU KURIOKA;ANDREW KAY
分类号 G06F12/14;G06F1/00;G06F21/72;G06F21/74;G06F21/77;G06F21/85;H04L9/00 主分类号 G06F12/14
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