发明名称 |
Method and apparatus for reducing latency in a digital signal processing device |
摘要 |
A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith. The processing circuitry is operatively configured to: (i) define a first subset of signal paths through the delay generation circuitry, the first subset including the zero delay signal path, and at least a second subset of signal paths through the delay generation circuitry, the second subset including one or more nonzero delay signal paths; (ii) remove an idle delay from all signal paths in the second subset, such that a shortest nonzero delay signal path in the second subset becomes a zero delay signal path; and (iii) incorporate the idle delay with the processing circuitry.
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申请公布号 |
US7107301(B2) |
申请公布日期 |
2006.09.12 |
申请号 |
US20020095206 |
申请日期 |
2002.03.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
RYLOV SERGEY V.;RYLYAKOV ALEXANDER V.;TIERNO JOSE A. |
分类号 |
G06F17/17;G06F17/10;H03H17/02;H03H17/06;H03K5/00 |
主分类号 |
G06F17/17 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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