| 摘要 |
A method and apparatus for fabricating a three dimensional array of semiconductor chips is disclosed. The method uses a multiple step fabrication process that automates the surface mounting of semiconductor chips with unique chip carriers to achieve the three dimensional array of chips. The method includes a step of depositing solder on a multitude of chip carriers at one time, placing the chip carriers with chips on a printed circuit board and then running the board with chips and carriers arranged in a three dimensional array through a single reflow oven to complete a single reflow process to permanently connect all of the components. The apparatus includes a unique chip carrier pallet and print fixture pedestal that work in combination to position the chip carriers for the automatic deposition of solder on a multitude of carriers at once and then position them for addition to the circuit board.
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