发明名称 Design method and apparatus for a semiconductor integrated circuit comprising checkers verifying the interface between circuit blocks
摘要 A functional block for verifying correct interface operation of any functional block is generated from interface description and installed on a LSI chip. To accomplish this, from the interface description, hardware description of a synthesizable interface checker is generated. Means for selecting interface functions to be checked is provided, thereby making it possible to reduce the overhead of circuits to be installed on the LSI.
申请公布号 US7107569(B2) 申请公布日期 2006.09.12
申请号 US20040770479 申请日期 2004.02.04
申请人 HITACHI, LTD. 发明人 ITO MASAKI
分类号 G06F17/50;G06F11/25;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F17/50
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