| 摘要 |
A stop and release circuit of a sync signal, to temporarily suspend or interrupt the sync signal, the input sync signal having a plurality of leading edges and a plurality of trailing edges, the circuit including a first divider that receives the input sync signal and supplies a first signal made up of the sync signal divided by two starting from a leading edge, a second divider that receives the inverse input sync signal and supplies a second signal made up of the sync signal divided by two starting from a trailing edge, an exclusive OR circuit that receives the first signal and the second signal and that supplies an output sync signal, a stop circuit for the first divider and the second divider, and an asynchronous command signal generated by the stop circuit for the temporary interruption of the output sync signal.
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