发明名称 |
Decision-feedback equalization clocking apparatus and method |
摘要 |
A decision feedback equalization ("DFE") technique is suitable for use in a serializer-deserializer ("SERDES") receiver in an integrated circuit (IC). The IC has a summing node coupled to a return-to-zero ("RTZ") data latch register. The RTZ data latch register has a first ("even") series of RTZ data latches and a second ("odd") series of RTZ data latches. A first even tap is coupled to the first even RTZ data latch and provides a feedback signal to the summing node on a first portion of a local clock cycle. A first odd tap is coupled to the first odd RTZ data latch and provides an odd feedback signal to the summing node on a second portion of the local clock cycle.
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申请公布号 |
US7106099(B1) |
申请公布日期 |
2006.09.12 |
申请号 |
US20040970969 |
申请日期 |
2004.10.22 |
申请人 |
XILINX, INC. |
发明人 |
NIX MICHAEL A. |
分类号 |
G06F7/38;H03H7/30;H03H7/40;H03K5/159;H03K19/177 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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