| 摘要 |
PROBLEM TO BE SOLVED: To improve an operation frequency in a system while realizing a pipeline type bus. SOLUTION: A master M1 is provided with a flip-flop F1 for outputting a ready signal Ready_1dl obtained by delaying a ready signal Ready supplied from a slave S1 side only by one cycle to supply the ready signal Ready_1dl as the entire control signal C1 to each block in the master M1. The post stage of an output side bus interface B2 is provided with timing compensation circuits H1 to H3 for respectively compensating the timing of an address signal Address, a control signal Control and write data WR_DATA outputted from the master M1. COPYRIGHT: (C)2006,JPO&NCIPI
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