| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To prevent any surplus margin from being set at the time of executing timing analysis by setting a margin for the delay fluctuation of a data path and a clock path. <P>SOLUTION: The margin coefficients of the delay fluctuation of a data path are decided according to the wideness of an arrangement region on the chip of each cell in the path of a data path, and the margin coefficients of the delay fluctuation of a clock path are decided according to the wideness of an arrangement area on the chip of each cell in the path of the clock path. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
