| 摘要 |
<P>PROBLEM TO BE SOLVED: To smoothly and stably switch the clock boards of an operation system and a standby system by accurately matching the phases of a master clock board and a slave clock board even in the case that a comparison frequency in a phase comparator is low and the cut-off of a loop response to jitters is extremely low, regarding the phase matching circuit of the clock board. <P>SOLUTION: Clock signals outputted from the master clock board and the slave clock board respectively are inputted to the phase comparator 1-1, and the phase difference signal of a voltage corresponding to a phase difference outputted from the phase comparator 1-1 is made to pass through a low-pass filter 1-2 and then inputted to a control part 1-3. The control part 1-3 outputs phase control signals for matching the phase on a slave clock board side with the phase on a master clock board side corresponding to the phase difference signals to phase matching PLL circuits 1-4 and 1-4', and the phase matching PLL circuits 1-4 and 1-4' control the phases of the respective clock signals according to the phase control signals and output them. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
