| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a microcomputer capable of executing interrupt processing without slippage of one cycle. <P>SOLUTION: An interrupt processing program 20 to be executed by a CPU 2 is described so that a plurality of nop instructions are arranged between the top and just before an instruction for starting substantial interrupt processing. An execution part 8 of the CPU 2 outputs, in execution of a special instruction, an interrupt retention signal according to a surplus time of its execution time exceeding that of a general instruction to the outside. An interrupt control part 10 increases, when the interrupt retention signal is outputted by the execution part 8 at the point of time when an interrupt request occurs, the fetch address value of instruction to the interrupt processing program 20 according to the output period of the signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
