发明名称 Control circuit and control method
摘要 The present invention aims to prefetch data which is stored in a cache memory and whose probability of access is high by replacing data whose probability of access is low. On discriminating a cache miss of target data which is used for an operation process performed by an operation processing unit, a cache hit discriminating unit obtains the target data from a main memory. Further, when the cache hit discriminating unit discriminates a cache hit, an invalid data discriminating unit discriminates a cache line including the target data is the same as the one including data which has been used for the previous operation process. Then, when the invalid data discriminating unit discriminates the cache line including the target data is different from the cache line including the data used for the previous operation process, a prefetch controlling unit prefetches the data by replacing data stored in the main memory with the cache line including the data used for the previous operation process.
申请公布号 US2006200631(A1) 申请公布日期 2006.09.07
申请号 US20050068862 申请日期 2005.03.02
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 SEKI SEIJI;KAMEMARU TOSHIHISA;NEGISHI HIROYASU;KOBARA JUNKO
分类号 G06F13/28 主分类号 G06F13/28
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