| 摘要 |
A method, algorithm, software, architecture, circuit, and/or system for detecting an idle condition and maintaining a frequency of a clock/data recovery circuit are disclosed. In one embodiment, a method of maintaining a frequency of a clock/data recovery circuit can include the steps of: (i) comparing a difference value from a differential signal with a predetermined threshold (or value); (ii) controlling a variable frequency oscillator (VFO) with a frequency detector when the difference value is less than the threshold for at least a predetermined integration time; and (iii) controlling the VFO with a phase detector receiving the differential signal when the difference value is greater than the threshold. Embodiments of the present invention can advantageously provide a reliable and simplified design approach for clock data recovery (CDR) circuits operable with low power mode transmitters.
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