| 摘要 |
A digital encoder having a dynamic element matching (DEM) processor is divided into a master DEM circuit and N slave DEM circuits. The master DEM circuit encodes a multibit digital input signal (IN 0 ) into parallel codes (C 1 ) corresponding to the coefficient of a plurality of output nodes on the basis of a prescribed DEM algorithm. Each of the N slave DEM means ( 2 ) has 3 or more output nodes. Code (C 1 ) from the master DEM circuit is encoded into parallel codes (C 2 ) with the same weighting for each code and corresponding to the configuration of the 3 or more output nodes on the basis of a prescribed DEM algorithm, and the obtained parallel codes are output in parallel from 3 or more output nodes.
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