发明名称 |
A semiconductor memory module and a multi-layer circuit bord for |
摘要 |
A method and apparatus for implementing a selectively operable clock booster for DDR memory and other logic modules, which utilize partially-defective memory parts or a combination of partially-defective and flawless memory parts. The method and apparatus include an improved clocking method and system, which enables the use of partially-defective memory parts without distorting the clock signal. In one embodiment, a Phase-Locked Loop circuit and a clock patching network are used to significantly reduce clock distortion on a memory module. |
申请公布号 |
EP1699056(A1) |
申请公布日期 |
2006.09.06 |
申请号 |
EP20060115412 |
申请日期 |
2003.02.24 |
申请人 |
CELETRONIX INTERNATIONAL, LTD |
发明人 |
PEDDLE, CHARLES, L. |
分类号 |
G11C29/00;G11C5/06;H01L21/66;H01L23/00;H05K1/00;H05K1/18;H05K3/22 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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