发明名称 Semiconductor memory apparatus
摘要 A semiconductor memory apparatus that accelerates the reading of data is provided with a memory cell, bit lines each sectioned into at least two portions, a device for reading data from a memory cell, each provided in between and connecting sectioned bit lines, and a device for connecting one of divided bit lines to the device for reading data or disconnecting connected one of sectioned bit lines from the device for reading data, depending on the position of the memory cell to be read.
申请公布号 US7102928(B2) 申请公布日期 2006.09.05
申请号 US20020304762 申请日期 2002.11.27
申请人 KAWAMURA SHOUICHI 发明人 KAWAMURA SHOUICHI
分类号 G11C16/00;G11C16/04;G11C16/24;G11C16/26 主分类号 G11C16/00
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